1. Field of the Invention
This invention relates generally to a microstrip-to-microstrip RF transition circuit and, more particularly, to a microstrip-to-microstrip RF transition circuit for a semiconductor wafer that employs an RF microstrip to a co-planar waveguide (CPW) transition.
2. Discussion of the Related Art
Microelectro-mechanical switches (MEMS) used for RF applications is a technology area that has potential for providing a major impact on existing RF architectures in sensors and communications devices by reducing the weight, cost, size and power dissipation in these devices, possibly by a few orders of magnitude. Key devices for existing RF architectures include switches in radar systems and filters in communications systems. However, while MEMS technology has demonstrated the potential to revolutionize such devices, MEMS devices have not been specifically designed for performance in harsh environments, typically required for military applications, such as unmanned aerial vehicles (UAV) and national missile defense (NMD) systems. Particularly, MEMS technology requires further development in order to be able to provide effective performance under large temperature variations, strong vibrations and other extreme environmental conditions.
An appropriate packaging scheme that combines the properties of traditional high-speed packages and compatibility with planar technology offers a solution to this issue. Packaging is one of the most critical parts of the RF and MEMS fabrication process. Packaging is the most expensive step in the production line and will ultimately determine the performance and longevity of the device.
A large number of publications exist relating to RF MEMS based circuits, including phase shifters, single-pole multiple-through circuits, tunable filters, matching networks, etc. Many of these circuits have been designed based on a microstrip line configuration. Therefore, in order to develop a compatible on-wafer packaging scheme, a microstrip-to-microstrip transition needs to be provided. Such a transition for a MEMS is disclosed in U.S. Pat. No. 6,696,645 describing a coplanar waveguide (CPW)-to-CPW transition. The transition needs to be as broadband as possible, with minimum insertion loss and no parasitic resonance up to 50 GHz.
It is an important design consideration for a broadband microstrip-to-microstrip transition to maintain a characteristic impedance of the transition at 50Ω, especially at high frequency (>5 GHz). The 50Ω characteristic impedance through the transition is necessary to minimize signal reflections that would otherwise provide signal loss and degrade device performance. The design problem occurs because of the need for a wider microstrip line, which provides a lower impedance, in order to accommodate for the anisotropic etching of the vias through a semiconductor silicon wafer. When silicon is etched in potassium hydroxide or tetramethyl ammonia hydroxide, the etch rate of the <100> crystal plane is much higher than the etch rate of the <111> plane. This means that the final etched structure has a pyramidal shape found in the <111> planes of the silicon crystal. The angle between the <111> and the <100> planes is 54.74°. Other semiconductor wafer materials, such as GaAs, InP, etc., have similar anisotropic etching profiles. Therefore, in order to get a 20×20 μm square at the bottom of the via, a 160×160 μm square at the top of the via is required. This means that the width of the microstrip line needs to be at least 200 μm at the top of the via to accommodate for the size of the top of the vias. The wider microstrip line has a decreased characteristic impedance (approximately 25-30Ω). This mismatch increases the return loss of a back-to-back transition, thus reducing the overall bandwidth of the structure.
FIG. 1 is a perspective view of a microstrip transition circuit 10 that illustrates this problem. The transition circuit 10 includes an upper microstrip line 12, a lower microstrip line 14, an upper ground plane 16 and a lower ground plane 18. A top semiconductor wafer (not shown), such as a silicon wafer, would be provided between the microstrip line 12 and the ground plane 16 and a bottom semiconductor wafer (not shown), such as a silicon wafer, would be provided between the microstrip line 14 and the ground plane 18, both of which have been removed for clarity purposes. The microstrip line 12 is patterned on a top surface of the top semiconductor wafer, the upper ground plane 16 is patterned on the bottom surface of the top semiconductor wafer, the microstrip line 14 is patterned on the top surface of the bottom semiconductor wafer, and the lower ground plane 18 is patterned on the bottom surface of the bottom semiconductor wafer.
A signal via 20 is formed through the top semiconductor wafer and is in electrical contact with the microstrip lines 12 and 14. Two ground vias 22 and 24 are formed through the bottom semiconductor wafer and provide an electrical contact between the upper ground plane 16 and the lower ground plane 18. The vias 20, 22 and 24 have a “pyrmidical shape” from top to bottom because of the anisotropic etch rates through the crystal planes of silicon when the opening for the vias 20, 22 and 24 are formed, as discussed above. The microstrip lines 12 and 14 and the vias 20, 22 and 24 would be made of a suitable metal, as would be well understood to those skilled in the art.
Typically, the thickness of the semiconductor wafers is about 100 μm because this is the minimum wafer thickness for current wafer fabrication processes. It is desirable that the semiconductor wafers be as thin as possible so that the parasitic inductances generated by the vias 20, 22 and 24 is as minimal as possible. When the openings for the vias 20, 22 and 24 are etched for a wafer of this thickness, the timing of the etch produces about a 160×160 μm metallized square at the top end of the vias 20, 22 and 24 so that the etch produces about a 20×20 μm square at the bottom end of the vias 20, 22 and 24. The size of the top end of the vias 20, 22 and 24 ensures that the openings for the vias 20, 22 and 24 will be formed all the way through the thickness of the wafer.
The width of the microstrip line 12 is about 80 μm to provide the desired 50 Ω. However, a widened portion 26 of the microstrip line 20 that makes electrical contact with the top end of the via 20 is wider than the metallized square at the top of the via 20 to provide a suitable electrical contact and the proper orientation and alignment. For the dimensions being discussed herein, the width of the widened portion 26 would be between 200 and 220 μm. Because the wider portion 26 is wider than the rest of the microstrip line 12, it has a different characteristic impedance, typically 25-30Ω. A tapered transition 28 between the widened portion 26 and the rest of the microstrip line 12 minimizes reflections provided by the change in the characteristic impedance, but does not eliminate them. Thus, significant signal loss occurs at the transition between the microstrip line 12 and the via 20, especially at high frequencies. The microstrip line 14 includes the same size transition to a widened portion 46 at the bottom end of the via 20 so as to maintain the 25-30Ω characteristic impedance.